vlib work
vlib riviera

vlib riviera/xil_defaultlib

vmap xil_defaultlib riviera/xil_defaultlib

vlog -work xil_defaultlib  -v2k5 \
"../../../bd/design_1/ipshared/41bd/CPU_1/CPU_1.srcs/sources_1/new/ALU_control.v" \
"../../../bd/design_1/ip/design_1_ALU_control_0_0/sim/design_1_ALU_control_0_0.v" \
"../../../bd/design_1/ipshared/f223/CPU_1/CPU_1.srcs/sources_1/new/control.v" \
"../../../bd/design_1/ip/design_1_control_0_0/sim/design_1_control_0_0.v" \
"../../../bd/design_1/ipshared/e098/CPU_1/CPU_1.srcs/sources_1/new/ALU.v" \
"../../../bd/design_1/ip/design_1_ALU_0_0/sim/design_1_ALU_0_0.v" \
"../../../bd/design_1/ipshared/6521/CPU_1/CPU_1.srcs/sources_1/new/Registers.v" \
"../../../bd/design_1/ip/design_1_Registers_0_0/sim/design_1_Registers_0_0.v" \
"../../../../project_1.srcs/sources_1/bd/Ex5_CPU/Instruction memory/CPU_1/CPU_1.srcs/sources_1/new/instruction_memory.v" \
"../../../bd/design_1/ip/design_1_instruction_memory_0_0/sim/design_1_instruction_memory_0_0.v" \
"../../../bd/design_1/ipshared/2094/CPU_1/CPU_1.srcs/sources_1/new/PC.v" \
"../../../bd/design_1/ip/design_1_PC_0_0/sim/design_1_PC_0_0.v" \
"../../../bd/design_1/sim/design_1.v" \


vlog -work xil_defaultlib \
"glbl.v"

